1. Field of the Invention
The present invention relates to apparatus and methods for improving timing recovery of a system clock. In particular, the present invention relates to apparatus and methods for causing the frequency of a system clock produced by a timing recovery apparatus to be within a specified tolerance range during a timing recovery acquisition period for the system clock.
2. Description of Related Art
When a digital signal (such as, for example, a digital television signal) is encoded for transmission through a transmission medium, program clock references, representing particular values of an encoder counter clocked by a stable clock having a frequency which is proportional to the sampling frequency of the digital signal to be transmitted, are encoded together with the digital signal in data packets. Such encoding may be done, for example, in accordance with the MPEG encoding standard.
As part of a decoding process of the data packets, it is necessary to produce a system clock from the program clock references contained in the data packets. In the prior art, the system clock is produced with the aid of a timing recovery apparatus. Such an arrangement is shown in FIG. 1 (and will be discussed in greater detail below). See also page 5 and FIG. 1b of a paper submitted to the ISO-IEC by B. Haskell and A. Reibman entitled "Timing Recovery of Variable Bit Rate Video on ATM Networks" in July of 1992, identified as ISO-IEC/JTC1/SC29/WG11, MPEG92/396.
Generally speaking, a timing recovery apparatus is a feedback system which minimizes the difference (hereafter referred to as the frequency difference) between the frequency of the system clock produced by the timing recovery apparatus and the frequency (hereinafter referred to as the encoder counter clocked frequency) at which the encoder counter was clocked. As in any feedback system, the time needed to minimize the frequency difference is inversely proportional to the bandwidth of the timing recovery apparatus and proportional to the difference between the initial frequency of the system clock when it is first turned on, or turned to a new channel, and the encoder counter clocked frequency. The period of time needed to bring the frequency of the system clock from its initial frequency to a frequency which is (substantially) identical to the encoder counter clocked frequency is known as the timing recovery acquisition period. (It should be noted here that in practice the frequency of the system clock will not actually become equal to the encoder counter clocked frequency, but it will become very very close to it.)
An ideal timing recovery apparatus would produce a system clock having an initial frequency which is identical to the encoder counter clocked frequency, and the timing recovery apparatus acquisition period would be zero. However, a practical timing recovery apparatus according to the prior art produces a system clock with an initial frequency which may differ significantly from the encoder counter clocked frequency. Furthermore, during the lifetime of the timing recovery apparatus, the initial frequency of the system clock will change due to, inter alia, the aging of its electronic components. Such changes can increase the difference between the initial frequency of the system clock and the encoder counter clocked frequency.
Prior art timing recovery apparatus are designed for situations in which transmission of the data packets (including the program clock references) from a transmitter to a receiver involves a constant delay from one data packet to another. However, in many networks, including asynchronous transfer mode ("ATM") networks, this is not the case. In ATM networks, the delay time may vary as much as 1 ms.
The effect of varying delays is jitter in the frequency of the system clock. Excessive jitter in the frequency of the system clock can lead to errors in decoding the data contained in the data packets representing the digital signal which has been transmitted, preventing recovery of a replica of that digital signal (hereinafter referred to as the transmitted signal replica). Moreover, excessive jitter in the frequency of the system clock can also lead to errors in deriving additional signals from the system clock and the transmitted signal replica which will result in inoperable additional signals. An example of additional signals which can be derived from the system clock and the transmitted signal replica are the components of a television signal used in a conventional (e.g., NTSC) television system.
In accordance with the prior art, the way to achieve low jitter in the frequency of the system clock produced by a timing recovery apparatus is to limit its bandwidth. This, however, results in the timing recovery acquisition period being very long.
During very long timing recovery acquisition periods, the frequency of the system clock will more than likely operate, for some period of time, outside the specified tolerance range in which operable additional signals can be derived from the system clock and the transmitted signal replica. Moreover, in certain situations, there may also be periods of time during long timing recovery acquisition periods in which the frequency of the system clock will not operate within the specified tolerance range necessary for proper decoding of the data representing the digital signal which has been transmitted to obtain a (transmitted signal) replica for that signal.
It should be noted that the specified tolerance range in which the frequency of the system clock must operate to properly decode the data representing the digital signal which has been transmitted to obtain a (transmitted signal) replica for that signal is often broader, i.e., larger, than and encompasses the specified tolerance range for deriving additional signals from the system clock and the transmitted signal replica which will operate properly. Hence, if the frequency of the system clock operates within the specified tolerance range needed from deriving operable additional signals from the system clock and the transmitted signal replica, it is assumed to operate within the specified tolerance range necessary for proper decoding of the data representing the digital signal which has been transmitted to obtain a (transmitted signal) replica for that signal.